The present invention relates to a method for manufacturing polysilicon type thin film transistors, and more particularly to a method for manufacturing polysilicon type thin film transistors using impurity implantation.
A thin film transistor liquid crystal display device (TFT-LCD) is a liquid crystal display (LCD) that controls electric fields imparted to pixel electrodes by using a plurality of thin film transistors, each of which is disposed in a pixel. In a polysilicon type TFT-LCD having a polysilicon layer formed in an active region of a glass substrate, carrier mobility at transistor channels is higher than that of an amorphous silicon type TFT-LCD. Accordingly, on the glass substrate of the polysilicon type TFT-LCD, transistor elements of an integrated circuit (IC) for use in a driving circuit can be formed with transistor elements for switching the pixel electrodes. Therefore, the process cost for manufacturing the LCD as well as the electric power operating the LCD can be reduced.
Generally, the driving circuit of the polysilicon type TFT-LCD includes n-type thin film transistors and p-type thin film transistors. Accordingly, in order to form the IC for the driving circuit on the glass substrate, it is necessary to form a plurality of thin film transistors, each of which has different impurity type, which the whole manufacturing process of polysilicon type TFT-LCD.
In addition source/drain electrodes of the polysilicon type TFT LCD are generally formed by a generation implantation or doping. At this time, if a heavily doped implantation is carried out by a high ion energy of more than 90 keV, most of the energy generated by the high ion energy is transformed into heat, which increases the temperature of the glass substrate beyond its limit, thereby stopping the manufacturing process. Also, the photoresist layer may be burnt. In such a case, photoresist is adhered to the glass substrate and cannot be removed by high energy generated by impingement of ions during the ion implantation. The photoresist is generally used as an ion implantation mask. In order to prevent the photoresist burning, a Cr mask may be formed as a subsidiary gate pattern on an Al-contained gate layer, instead of the photoresist ion implantation mask. However, the Cr mask still may not be completely removed after the ion implantation. Also, during the subsequent annealing process, the Cr mask may react with Al of the Al-contained metal gate layer and form pinholes.
When an ion implantation is carried out, an annealing is required to cure the damage done to a polysilicon layer in an active region during the ion implantation and to activate implanted ions to provide TFT elements proper efficiency. Laser equipment is generally used in generating a high temperature in a moment during the annealing. However, since the laser equipment and subsidiary parts are costly articles of consumption, there is a problem that the product cost may increase.
It is an object of the present invention to provide an improved method for manufacturing polysilicon type thin film transistors that can reduce the product cost by using a thermal annealing instead of a costly laser annealing.
It is another object of the present invention to provide an improved method for manufacturing polysilicon type thin film transistors that can prevent an quality problem such as a photoresist burning during the manufacturing process.
It is another object of the present invention to provide a method for manufacturing polysilicon type thin film transistors that can reduce the number of the manufacturing process without causing a quality problem.
These and other objects are provided, according to the present invention, by a method for manufacturing polysilicon type thin film transistors comprising the steps of forming a polysilicon layer on a substrate, forming a gate insulating layer on the polysilicon layer, forming a gate pattern on the gate insulating layer, forming source/drain regions in the polysilicon layer of the substrate over which the gate pattern is formed, by implanting impurities in the polysilicon layer, forming a cover layer over the substrate over which the gate pattern is formed, and performing a thermal annealing against the substrate over which the cover layer is formed.
The step of forming the gate pattern comprises forming a gate layer on the gate insulating layer, forming a photoresist pattern on the gate layer, and forming a gate pattern and a gate insulating layer pattern by etching the gate layer and the gate insulating layer by using a photoresist pattern as a mask, and the step of forming source/drain regions by implanting impurities uses the photoresist pattern as an ion implantation mask.
In a preferred embodiment of the invention, the cover layer can be formed of a silicon oxide layer or a silicon nitride layer. In case of the silicon oxide layer, the cover layer itself is formed as an interlayer insulating layer and the thermal annealing is carried out at a temperature of 400xc2x0 C.-500xc2x0 C. for more than 30 minutes.
Also, in case of the silicon nitride layer, the cover layer is formed to a thickness of 500 xc3x85-5000 xc3x85 and the thermal annealing is carried out at a temperature of 400xc2x0 C.-450xc2x0 C. for more than 30 minutes.
Alternatively, the thermal annealing can be carried out after forming an intermediate insulating layer on the cover layer, forming contact holes in the interlayer insulating layer, and forming a source/drain electrode layer over the substrate over which the contact holes are formed. The source/drain electrode layer forms data lines. Preferably, the source/drain electrode layer is composed of a double layered structure including a MoW layer as a lower layer, or a triple layered structure including MoW layers as upper and lower layers, rather than a sole Al layer in order to prevent spikes due to the diffusion since the doped polysilicon layer is disposed thereunder.
In the invention, it is preferable that the impurity implantation is carried out by a low energy ion implantation using an ion energy of below 30 keV. Also, a dose during the low energy ion implantation is preferably more than 1.0xc3x971015 ions/cm2. Generally, the low energy ion implantation is carried out directly on the polysilicon layer after removing the gate insulating layer.
In a driving circuit of a TFT-LCD to which the invention is applied, n-type transistors as well as p-type transistors are used. In this case, the step of forming the photoresist pattern, the step of forming the gate pattern and the gate insulating pattern by using the photoresist pattern as a mask, and the stop of forming source/drain regions by using the photoresist pattern as an ion implantation mask are carried out once p-type and n-type transistors are formed respectively. When p-type or n-hype transistors are formed, the other type of transistor regions are protected by the photoresist pattern. Also, the invention includes sub-steps for forming LDD regions and offset regions.
The method of the invention has better effects when using a low energy ion implantation than a general high energy ion implantation. As the high energy ion implantation is substituted with the low energy ion implantation, the dose of impurities can be increased and the required level of annealing lowered since the ion implantation is carried out after the polysilicon layer is exposed by removing a gate insulating layer. Therefore, it is possible to easily carry out a thermal annealing instead of a laser annealing.